1. Field of the Invention
The present invention relates to a method of layout of a driving chip of an liquid crystal display (LCD) and related LCD, and more particularly, to a layout method and related LCD capable of reducing the margin-area width of the bottom of the substrate of the LCD.
2. Description of the Prior Art
The advantages of a liquid crystal display (LCD) include light weight, less power consumption, and less radiation contamination. Thus, the LCD monitors have been widely applied to various portable electronic products, such as notebooks, PDAs, etc. Generally, the portable electronic products have to be designed as small as possible. Therefore, the prior art has already provided many layout methods for reducing layout sizes of the LCDs in the portable electronic products.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a prior art LCD 10 of a portable electronic device. The LCD 10 includes a substrate 100, a panel 1 02, and a driving chip 104. The panel 102 includes transistor switches controlled by the control signals of the driving chip 104. The driving chip 104, which is an integrated circuit (IC) integrated with a gate driver, a source driver, a power management chip, and a memory module, controls the panel 102 to display images. Both of the panel 102 and the driving chip 104 are formed on the substrate 100, and regions other than the panel 102 and the driving chip 104 in the substrate 100 are margin areas, which are usually utilized for wiring layout. Certainly, the smaller the margin areas occupy, the less the production cost is. Please refer to FIG. 2. FIG. 2 is a schematic diagram of prior art layout of the driving chip 104. In FIG. 2, a minimum height of the driving chip 104 is h1, and pins PL_1˜PL_n and PR_1˜PR_n of the driving chip 104, utilized for outputting gate driving signals, are set on the substrate 100 along a horizontal direction. Each of the wires RL_1˜RL_n and RR_1˜RR_n, utilized for transmitting the gate driving signals outputted from the pins PL_1˜PL_n and PR_1˜PR_n to the panel 102, is electronically coupled between one of the pins PL_1˜PL_n and PR_1˜PR_n and the panel 102. As shown in FIG. 2, each of the wires RL_1˜RL_n and RR_1˜RR_n begins from a pin, heads to the edge of the panel 102, and connects to a horizontal line of the panel 102 after a bend. In other words, each wire includes a bend on the substrate 100. As those skilled in the art recognized, in order to transmit signals effectively, bending angles of the wires RL_1˜RL_n and RR_1˜RR_n are restricted to be larger than a specific angle A. In such case, the distance between the panel 102 and the driving chip 104 must be larger than a minimum distance d1. If the distance between the panel 102 and the driving chip 104 is smaller than d1, the bending angles of the wires closer to the center of the driving chip 104, such as the wires RL_n, RL_(n−1), RR_n, and RR_(n−1), are smaller than the angle A, so that signals of the corresponding pins cannot be transmitted to the panel 102 efficiently. Therefore, the distance between the panel 102 and the driving chip 104 has to be larger than d1, and a width of the margin area below the panel 102 must be larger than (d1+h1).
Furthermore, please refer to FIG. 3. FIG. 3 is a schematic diagram of another prior art layout of the driving chip 104. In FIG. 3, the pins PL_1˜PL_m and PR_1 ˜PR_m of the driving chip 104 are set on the substrate 100 along a vertical direction, and the pins PL_(m+1)˜PL_n and PR_(m+1)˜PR_n are set on the substrate 100 along a horizontal direction. In comparison, layout of FIG. 3 moves a part of pins in FIG. 2 to the vertical direction of the driving chip 104. Hence, the number of pins along the horizontal direction of the driving chip 104 decreases, so that the minimum distance between the panel 102 and the driving chip 104 changes from d1 to d2. However, due to the pins PL_1˜PL_m and PR_1˜PR_m are set on the vertical direction of the driving chip 104, the height of the driving chip 104 changes from h1 to h2. In other words, reduction of width of the margin areas is limited. Thus, the layout shown in FIG. 3 is no great help for reducing the area of the substrate 100.
Therefore, no matter applying the layout of FIG. 2 or FIG. 3, the margin area of the bottom of the LCD 10 cannot be reduced effectively.